AT28HC256 |
RFQ for AT28HC256 |
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| Technical/Catalog Information | AT28HC256-12DM/883 |
| Vendor | Atmel |
| Category | Integrated Circuits (ICs) |
| Memory Type | EEPROM |
| Memory Size | 256K (32K x 8) |
| Speed | 120ns |
| Interface | Parallel |
| Package / Case | 28-CDIP |
| Packaging | Tube |
| Voltage - Supply | 4.5 V ~ 5.5 V |
| Operating Temperature | -55°C ~ 125°C |
| Format - Memory | EEPROMs - Parallel |
| Drawing Number | * |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | AT28HC256 12DM 883 AT28HC25612DM883 AT28HC256 12DM883 ND AT28HC25612DM883ND AT28HC256-12DM883 |
| Product | Manufacturers | Pack | D/C |
| AT28HC256 | Atmel | - | - |
The AT28HC256 is a high-performance Electrically Erasable and ProgrammableRead Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Man-ufactured with Atmel's advanced nonvolatile CMOS technology, the AT28HC256offers access times to 70 ns with power dissipation of just440 mW. When the AT28HC256 is deselected, the standbycurrent is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the reador write cycle without the need for external components.The device contains a 64-byte page register to allow writingof up to 64 bytes simultaneously. During a write cycle, theaddress and 1 to 64 bytes of data are internally latched,freeing the addresses and data bus for other operations.
Following the initiation of a write cycle, the device will auto-matically write the latched data using an internal controltimer. The end of a write cycle can be detected by DATA polling of I/O7 . Once the end of a write cycle has been
detected a new access for a read or write can begin.
Atmel's 28HC256 has additional features to ensure highquality and manufacturability. The device utilizes internal error correction for extended endurance and improved dataretention characteristics. An optional software data protec-tion mechanism is available to guard against inadvertentwrites. The device also includes an extra 64 bytes ofEEPROM for device identification or tracking.
Features |
| Fast Read Access Time - 70 nsAutomatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control TimerFast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum 1 to 64-Byte Page Write OperationLow Power Dissipation 80 mA Active Current 3 mA Standby CurrentHardware and Software Data ProtectionDATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 104or 105Cycles Data Retention: 10 YearsSingle 5V ± 10% SupplyCMOS and TTL Compatible Inputs and OutputsJEDEC Approved Byte-Wide PinoutFull Military, Commercial, and Industrial Temperature Ranges |